Photolithography is a process used in the fabrication of microelectronic devices and circuitry to selectively remove parts of a thin film or the bulk of a substrate. Photolithographic patterning tools use light to transfer a geometric pattern from a photo or template mask to light-sensitive photo resist located on the substrate. Thereafter, chemical processes may be used to engrave the resultant exposure pattern into the material underneath the photo resist.
Photolithographic patterning tools have inherent pitch patterning limitations as regards the patterning of lines and spaces. Consequently, as technologies move to smaller pitches, the pitches, employed in the implementation of such technologies, move beyond the patterning capability of existing patterning tools. Indirect patterning techniques are used to achieve pitches beyond the patterning capability of conventional patterning tools.
A conventional indirect patterning technique utilizes spacers to define lines and spaces in a wafer pattern. In this approach, the pitch of features of the template layer that define the location of the spacers are twice the final pitch of features of the final pattern and thus allows the final pattern to include features that are as much as half the minimum patterning pitch. A shortcoming of this approach is that in contrast to direct patterning approaches, the template mask image does not represent the final pattern and thus conventional layout verification tools can not be used to verify proper layout and hookup.
In addition, such approaches require the drawing of both a template layer pattern and a desired final wafer pattern. Because the technician is required to manually draw a template layer pattern as well as the desired final wafer pattern, the likelihood that wafer pattern errors will result is increased. This is especially true for wafer pattern errors that are not obvious from an inspection of the template pattern. Moreover, drawing both a template layer pattern and a desired final wafer pattern involves much more than double the work that is required where only the drawing of the template layer pattern is involved.
It should be appreciated that template layer work is not intuitive to a layout engineer and requires a detailed knowledge of patterning technology. Such knowledge is generally within the domain of the process technologist who typically does not possess the skill set of the layout engineer. Therefore, where conventional approaches are used, the artisans involved in the implementation of a design require additional training. The additional time that is required to train artisans involved in the design implementation process causes design flow delays. Accordingly, conventional approaches are inefficient and error prone and involve design flow delays that add to the cost and complexity of the manufacturing process.